The present invention relates generally to non-volatile integrated memory devices and more particularly to an improved sense amplifier and method of operating the same to quickly read data stored in a multi-state memory cell with a high degree of accuracy.
Non-volatile memories, such as electronically erasable programable read-only memories (EEPROM) or flash memories, are widely used in portable devices including devices lacking a mass data storage devices and a fixed source of power, such as cellular phones, handheld personal computers (PCs), portable music players and digital cameras.
Non-volatile memories are typically semiconductor devices having a number of memory cells each with a field effect transistor having a control-gate and an isolated or floating-gate that is electrically isolated from a source and a drain of the FET. Non-volatile memories program or store information by injecting charge on the floating gate to change a threshold voltage of the FET. The injected charge changes the threshold voltage of the FET from an intrinsic threshold voltage by an amount proportional to the charge. The new threshold voltage of the FET in the memory cell represents one or more bits of programmed data or information. For example, in a simple memory cell storing a single bit of data, the FET threshold voltage is either raised to a value near a high end of the threshold voltage range or maintained at a value near a low end. These two programmed threshold voltages represent a logical one or a logical zero. These voltages program the memory cell to turn on or off, respectively, when read conditions are established, thereby enabling a read operation to determine if data stored in the memory cell is a logical one or a logical zero.
To read the bit stored in a simple memory cell, an intermediate threshold voltage is applied to the FET and a resulting current compared with a reference current. A memory cell programmed to a high threshold voltage, a logical one, will conduct less current than the reference current, and a memory cell programmed to a low threshold voltage, a logical zero, will conduct more current than the reference current. The current comparison is accomplished with a circuit known as a sense amplifier or, more commonly, a sense amp. For a simple memory cell, the output of the sense amplifier is a one bit digital signal representing the logical state of the data stored in the memory cell.
More sophisticated non-volatile memories have multilevel or multi-state memory cells enabling the storage of more than one bit per memory cell. Storing more than one bit per memory cell requires that the threshold voltage space of the memory cell be divided or partitioned into multiple regions or memory states, each associated with one of several threshold voltages representing one of several possible bits or data states. For example, a multi-state memory cell capable of storing two bits of data requires a threshold space having four memory states, and a multi-state memory cell storing three bits of data requires partitioning the threshold space into eight memory states. Exemplary flash memories having such multi-state memory cells are described in U.S. Pat. Nos. 5,043,940 and 5,434,825, which patents are incorporated herein by reference.
To exploit the concept of non-volatile memories having multi-state memory cells fully, the memory states should be packed as closely together as possible, with minimal threshold voltage separation for margin/discrimination overhead. Thus, reading a multi-state memory cell requires that the sense amplifier precisely resolve the programmed threshold voltage with margins much smaller than the separation between available memory states. For example, given a multi-state memory cell having FETs with a two-volt threshold voltage space and four bits per memory cell (sixteen memory states per memory cell), each memory state is 125 mV wide, which requires the sense amplifier to resolve threshold voltages to within a few millivolts. Typically, the sense amplifier must be able to resolve thresholds to within about 10 mV or less.
In addition to resolving small voltage differences, performance requirements dictate that the sense amplifier be able to determine the programed threshold voltage within a very short time. This can be very critical in non-volatile memories using a closed loop write, where the programming operation is followed by a verify operation, in which the sense amplifier checks whether the threshold voltage of the memory cell being programmed has reached the desired value. These performance and resolution requirements are difficult to satisfy simultaneously. Often, performance must be sacrificed to improve resolution and vice versa.
FIG. 1 shows a prior art sensing circuit, commonly known as a current sensing circuit. A current mirroring circuit 10 and multiple sense amplifiers 15, generally one sense amplifier for each memory state, compare the current from memory cell 20 with multiple reference currents provided simultaneously by multiple reference current circuits 25. A predetermined fixed voltage, higher than a maximum programmed threshold voltage, is applied to the control gate of the memory cell being read. The resultant memory cell current is mirrored using a P-channel FET to multiple P-channel FETs as shown in FIG. 1. These multiple mirrored currents are compared to multiple reference currents by the multiple sense amps. The different reference currents are equal to current produced by programmed threshold voltages that correspond to boundaries of threshold voltage partitions. The digital outputs of the sense amps indicate the memory cell state.
While an improvement over earlier designs, this approach is not wholly satisfactory for a number of reasons. As arrays grow in size and have increasing numbers of memory cells, it is not feasible to provide the necessary current, generally on the order of tens of micro amperes (xcexcA), to mirror for the larger number of cells. Furthermore, it is difficult to read the cell state by distinguishing small current levels.
In a so-called voltage sensing approach, shown in FIGS. 2 and 3, a voltage (VBL) on a bit-line 28 of the memory cell 20 is pre-charged to a reference voltage (VPRE) using a pre-charge voltage VPRE. Optionally, bit-line 28 of the memory cell 20 is pre-charged through a cascode device 32. A control gate voltage (VCG) exceeding the maximum possible threshold voltage (VT) cell is applied to the control gate 28. VCG is chosen in relation to VT such that an erased memory cell will always conduct with that magnitude of VCG. After a period of time, xcex94t, VBL is compared with a trip or reference voltage (VTRP) using an inverter or comparator 30. Referring to FIG. 3, it is seen that if VBL is larger than VTRP after xcex94t, the cell 20 conducts less than an effective comparison current (ICOMP), and therefore VT is higher and the cell is programmed. It can be shown that a simplified approximate expression for the effective comparison current is:
ICOMP=CBL(VPRExe2x88x92VTRP)/(Avxc2x7xcex94t)
where AV is the voltage gain of the cascode device, and CBL is the bit-line capacitance.
If the memory cell 20 is a multilevel or multi-state memory cell, the VT can be determined more precisely by applying a sequence of different VCG voltages and comparing the resultant VBL voltages. For example, in one version of this approach known as half-stepping, a VCG of about half of a maximum possible VCG is applied. If the resultant VBL is less than VTRP, in a second iteration (or pass), a VCG that is half of the VCG applied in the first pass, or one-quarter of the maximum possible VCG is applied. If the resultant VBL is greater than expected, in the second or subsequent pass, a VCG that is 1.5xc2x7VCG applied in the first pass, or 75% of the maximum possible VCG is applied. The process continues until the VT is determined with sufficient precision.
While an improvement over earlier designs and methods for large arrays and/or small devices, this approach is not wholly satisfactory. For example, the effective comparison current is generally not constant due to variation in supply voltage, develop time (the time in which the intermediate threshold voltage is developed), or time variations in bit-line capacitance, as ICOMP varies with time per the above equation. For example, bit-line capacitance can change from the write time to the read time of the cell due to write or erase of other memory cells in a memory array coupled to the same bit-line. This change in capacitance can cause an offset in ICOMP, resulting in multi-state memory cell data being read incorrectly.
Another problem is that the difference between VPRE and VTRP can vary with temperature and with the voltage supply, especially when the comparator is a simple inverter. Further, measured time can vary due to variations in a clock chip (not shown), which is susceptible to variations in temperature and/or supply voltages.
A further constraint on designs of non-volatile memories having multi-state memory cells is power consumed by the sense amplifier during the read operation. Non-volatile memories using the approach described above often require hundreds of sense amplifiers working in parallel to read the multi-state memory cells with sufficient precision and speed. Such large numbers of sense amplifiers can consume a significant portion of the available power. Thus, the very low power budgets of today""s portable devices can put a severe constraint on sense amplifier design. For example, sense amps having cascode stages are desired for their increased gain. But cascode stages may not be practical because of an increased headroom required between voltage supply traces or head rails delivering high voltages from an external source. Non-volatile memories having high voltages from an on-chip voltage supply are available. However, these voltage supplies generally have a severely limited power capacity and consume too much power, especially in portable devices. Furthermore, the power available from on-chip voltage supplies is even more limited and must be conserved, especially to reduce chip heat dissipation. Thus, the shrinking power and voltage supplies in portable devices introduce limitations on sense amplifier designs.
Another important consideration in the design of sense amps is the chip or die area used by the sense amplifier. As noted above, to achieve satisfactory performance, a non-volatile memory having multi-state memory cells typically requires multiple sense amps on the chip. Thus, sense amplifiers can make up a significant fraction of the die area of the non-volatile memory.
Accordingly, there is a need for a non-volatile memory having multi-state memory cells with a sense amplifier capable of quickly reading data stored in the cell with a high degree of accuracy. There is a further need for a sense amplifier capable of reducing errors in reads due to due to low resolution. There is a still further need for a sense amplifier having a reduced power consumption, that makes efficient use of components to reduce cost and conserves chip space.
The present invention provides such sense amplifiers.
The present invention provides a sense amplifier with a pre-charged state set at the sense amplifier trip point. Use of such pre-charged trip point state provides an effective comparison current that is equal to a reference current, and substantially independent of variations in supply voltage, develop time, and capacitance of components of the sense amplifier, and advantageously reduces the time required for the sensing operation. In one embodiment, a pre-charge regenerative circuit is provided for the sense amplifier.
In one aspect, the present invention is directed to a sense amplifier for reading data stored in a multi-state memory cell in a non-volatile memory device. The sense amplifier includes a cascode device coupled to the drain of the memory cell FET and having a pre-charge circuit coupled to the cascode device. The cascode device is preferably a FET having a source coupled to the drain of the memory cell FET and having a drain coupled to the pre-charge circuit. The cascode device increases the resolution of the sense amplifier during a read operation, and isolates other components of the sense amplifier from a high voltage applied to the memory cell during a write operation. The pre-charge circuit is configured to pre-charge a node of the cascode device. The cascode device pre-charges the bit-line coupled to the memory cell to a pre-charge state during a pre-charge operation when the sense amplifier is in a pre-charge mode. Such pre-charging advantageously reduces time required to read the multi-state memory cell.
In another aspect, the pre-charge circuit includes a unity gain buffer to whose input a predetermined reference voltage is applied, and includes an output coupled to the node of the cascode device. The pre-charge circuit provides a bias current (IBIAS) to the cascode device to pre-charge the bit-line through the cascode device to the predetermined reference voltage. The pre-charge circuit can further include a transistor switch to couple the unity gain buffer to the cascode device when the sense amplifier is in the pre-charge mode, and to decouple it from the cascode device when the sense amplifier is in a develop mode. In develop mode, a reference current circuit provides a reference current (IREF) to the cascode device, and a difference between IREF and a current through the memory cell (ICELL) causes a change in the voltage applied to the cascode device from the predetermined reference voltage, thereby developing a voltage signal representing data stored in the memory cell.
In yet another aspect, the pre-charge circuit is re-configured as a regeneration circuit when the sense amplifier is in a regeneration mode to amplify the voltage signal developed during the develop mode. The pre-charged state is selected to put the regeneration circuit into a meta-stable state set at a trip point of the sense amplifier. Use of such a pre-charged state at the trip point produces an effective comparison current that is equal to a reference current, and substantially independent from factors such as bit-line capacitance, supply voltage, and develop time. Such setting of the pre-charge state at the trip point of the sense amplifier can speed up the read operation.
In still another aspect, a method of operating a sense amplifier according to the present invention to read data stored in a multi-state memory cell is provided. A pre-charge circuit is coupled to the cascode device, and the bit-line pre-charged through the cascode device to a predetermined reference voltage. The pre-charge circuit is de-coupled from the cascode device, and a voltage signal representing data stored in the memory cell is developed. The pre-charge circuit is reconfigured as a regeneration circuit to amplify the voltage signal.
The pre-charge circuit preferably includes a unity gain buffer having an output coupled to the cascode device through a transistor switch. Coupling the pre-charge circuit to the cascode device is accomplished by applying a control signal to turn-on the transistor switch. Pre-charging the bit-line through the cascode device to the predetermined reference voltage involves (i) applying the predetermined reference voltage to an input of the unity gain buffer; and (ii) applying a bias current IBIAS from the unity gain buffer to a node of the cascode device to pre-charge the bit-line to the predetermined reference voltage. The sense amplifier further includes a reference current circuit to provide a reference current (IREF) to the cascode device. The cascode device is pre-charged by applying both IREF and IBIAS simultaneously to the cascode device. Developing a voltage signal is accomplished by allowing a difference between IREF and a current through the memory cell (ICELL) to change the predetermined reference voltage to which the bit-line is charged.
Reconfiguring the pre-charge circuit as a regeneration circuit involves forming an amplifier having a positive feedback loop. The voltage signal is then amplified using the amplifier. To further reduce time required to read the multi-state memory cell the pre-charge is preferably reconfigured to form the regeneration circuit while the voltage signal is being developed.